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74LV377 Octal D-type flip-flop with data enable; positive edge-trigger
Product specification Supersedes data of 1997 Mar 04 IC24 Data Handbook 1998 Jun 10
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
FEATURES
* Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, * Ideal for addressable register applications * Data enable for address and data synchronization applications * Eight positive-edge triggered D-type flip-flops * Output capability: standard * ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV377 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT377. The 74LV377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.
CONDITIONS CL = 15pF VCC = 3.3V 3 3V
TYPICAL 13 77 3.5 20
UNIT ns MHz pF pF
Notes 1 and 2
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV377 N 74LV377 D 74LV377 DB 74LV377 PW NORTH AMERICA 74LV377 N 74LV377 D 74LV377 DB 74LV377PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN DESCRIPTION
PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL E Q0 to Q7 D0 to D7 GND CP VCC FUNCTION Data enable input (active-LOW) flip-flop outputs Data inputs Ground (0V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
FUNCTION TABLE
OPERATING MODES Load ``1'' Load ``0'' Hold (do nothing) H h L l X INPUTS CP X E l l h H Dn h l X X OUTPUTS Qn H L No change No change
= HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH CP transition = Don't care
1998 Jun 10
2
853-1935 19545
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
11 E Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 3 1
1C2 G1
2D
2
4 7 8 13 14 17 18
5 6 9 12 15 16 19
SV00667
SV00669
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
11 3 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 E CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 1 11 1 E CP 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
SV00668
SV00670
1998 Jun 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - TYP 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C
tr, tf
Input rise and fall times
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK IOK IO IGND, ICC Tstg PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with -standard outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +4.6 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C
Pt t tot
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V VIL LOW l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V; VI = VIH or VIL; -IO = 100A HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 6mA VCC = 1.2V; VI = VIH or VIL; IO = 100A LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs II ICC ICC Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V 1.8 2.5 2.8 2.20 V 0.9 1.4 2.0 0.3 0.6 0.8 -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC - 0.6V
1.0 20.0 500
1.0 160 850
A A A
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 Jun 10
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL =1KW SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH / Propagation delay g y CP to Qn Figure 1 2.0 2.7 3.0 to 3.6 2.0 tW Cl k pulse width idth Clock l HIGH or LOW Figure 2 2.7 3.0 to 3.6 1.2 tsu Set-up time Dn to CP Figure 2 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time E to CP Figure 2 2.0 2.7 3.0 to 3.6 1.2 th Hold time Dn to CP Figure 2 2.0 2.7 3.0 to 3.6 1.2 th Hold time E to CP Figure 2 2.0 2.7 3.0 to 3.6 2.0 fmax Mi lk Maximum clock ulse pulse frequency Figure 1 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. MIN - - - - 34 25 20 - 22 16 13 - 22 16 13 - 5 5 5 - 5 5 5 14 19 24 LIMITS -40 to +85 C TYP1 80 27 20 152 9 6 52 25 9 6 52 10 4 3 22 -15 -5 -4 -32 -5 -2 -2 -12 40 58 702 MAX - 51 38 30 - - - - - - - - - - - - - - - - - - - - - - -40 to +125 C MIN - - - - 41 30 24 - 26 19 15 - 26 19 15 - 5 5 5 - 5 5 5 12 16 20 MAX - 61 45 36 - - - - - - - - - - - - - - - - - - - - - - MHz ns ns ns ns ns ns UNIT
1998 Jun 10
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V VM = 0.5V * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load.
1/fmax VCC CP INPUT GND tW tPHL VOH Qn OUTPUT VOL VM tPLH VM
TEST CIRCUIT
VCC
VI PULSE GENERATOR RT D.U.T.
VO
50pF CL
RL = 1k
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. TEST tPLH/tPHL VCC < 2.7V 2.7-3.6V VI VCC 2.7V
SV00707
Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
VCC E INPUT
GND
VCC Dn INPUT GND VCC CP INPUT GND
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 2. Data set-up and hold times from the data input (Dn) and from the enable input (E) to the clock (CP).
1998 Jun 10
EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE
VM th th tsu tsu STABLE VM tsu th tW VM
SV00901
Figure 3.
Load circuitry for switching times
SV00671
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 Jun 10
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 Jun 10
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 Jun 10
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 Jun 10
11
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04449
Philips Semiconductors
1998 Jun 10 12

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